The embodiments described below involve the developing and ever-expanding field of computer systems and microprocessors. Modern microprocessors often now include a pipeline with numerous stages so that different instructions may be at different stages at the same time of operation. Moreover, some microprocessors include more than one pipeline in this manner and, therefore, can perform more than one instruction execution at a time. Naturally, the ability to execute more than one instruction at a time provides vast increases in processor speed and, therefore, is highly desirable.
The stages of a microprocessor pipeline provides different functions on an instruction as it passes through each pipeline stage. Typically, a pipeline commences with an instruction fetch stage, which retrieves one or more instructions which are encoded according to a single required format according to the instruction set architecture ("ISA") of the given microprocessor. After the fetch stage, a pipeline often includes various decode stages which receive a fetched instruction and convert it, which is sometimes referred to as decompressing it, to a form which can be executed. This executable form may then pass through one or more stages, such as a scheduling stage, and then is connected to an execution stage for execution. After execution, the pipeline graduates the instruction. In addition, the result of the instruction, if any, may be written to some store such as a register file. This last operation is commonly referred to as write back.
While the above approach provides beneficial in many respects, the present inventors have discovered various of its limitations. For example, the decode stages of the pipeline are typically limited to a single ISA. Thus, those decode stages and the microprocessor using them are necessarily limited to programs written for that ISA, and entire programs or program threads written for a different ISA will not properly function on this limited-scope microprocessor.
In view of the above as well as other considerations, there arises a need to address the drawbacks of the prior art and to provide a microprocessor with circuits, systems, and methods which allow proper operation in instances such as using instructions from more than one ISA, or where it is desirable for different instructions to pass through different pipeline stages.